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У меня USB 2.0 Pinnacle PCTV deluxe.
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General description
The SAA7114 is a video capture device for applications at the image port of VGA controllers.
The SAA7114 is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7114 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video phone codec. At the so called image port (I port) the SAA7114 supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.
The target application for the SAA7114 is to capture and scale video images, to be provided as a digital video stream through the image port of a VGA controller, for display via the frame buffer of the VGA, or for capture to system memory.
In parallel SAA7114 also incorporates provisions for capturing the serially coded data in the vertical blanking interval (VBI data). Two principal functions are available:
To capture raw video samples, after interpolation to the required output data rate, via the scaler
A versatile data slicer (data recovery) unit.
The SAA7114 also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback.
The circuit is I²C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).
Features
Video decoder
Six analog inputs, internal analog source selectors, e.g. 6 x CVBS or (2 x Y/C and 2 x CVBS) or (1 x Y/C and 4 x CVBS)
Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters
Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel
Automatic Clamp Control (ACC) for CVBS, Y and C
Switchable white peak control
Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the expansion port
On-chip line-locked clock generation in accordance with “ITU 601”
Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
Requires only one crystal (32.11 or 24.576 MHz) for all standards
Horizontal and vertical sync detection
Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards
Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation:
Increased luminance and chrominance bandwidth for all PAL and NTSC standards
Reduced cross colour and cross luminance artefacts
PAL delay line for correcting PAL phase errors
Independent Brightness Contrast Saturation (BCS) adjustment for decoder part
User programmable sharpness control
Independent gain and offset adjustment for raw data path.
Video scaler
Horizontal and vertical downscaling and upscaling to randomly sized windows
Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (it should be noted that the H and V zoom are restricted by the transfer data rates)
Anti-alias and accumulating filter for horizontal scaling
Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames
Fieldwise switching between decoder part and expansion port (X port) input
Brightness, contrast and saturation controls for scaled outputs.
Vertical Blanking Interval (VBI) data decoder and slicer
Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS), etc.
Audio clock generation
Generation of a field-locked audio master clock to support a constant number of audio clocks per video field
Generation of an audio serial and left/right (channel) clock signal.
Digital I/O interfaces
Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-CB -CR :
Output from decoder part, real-time and unscaled
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals
Discontinuous data streams supported
32-word x 4-byte FIFO register for video output data
28-word x 4-byte FIFO register for decoded VBI data output
Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-CB -CR output
Scaled 8-bit luminance only and raw CVBS data output
Sliced, decoded VBI data output.
Miscellaneous
Power-on control
5 V tolerant digital inputs and I/O ports
Software controlled power saving standby modes supported
Programming via serial I²C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s
Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”.
